DFT Engineer

• 04 August 2026 • 80 - 100% • Indefinite duration • English (Intermediate) • Rue des Jordils 1B, 1025 St-Sulpice VD • Log in to see the jobup.ch salary estimate Job Description Challenges are our engine, innovation our vocation. At Kandou, we are a team of passionate and accomplished professionals leaving their mark on the semiconductor industry. We are an innovative leader in high-speed, low-power chip-to-chip interconnect solutions, essential to the evolution of the electronics industry, continuously developing to meet the requirements not only of today's customers, but also tomorrow's. If you love being part of a rapidly expanding technology company and are motivated by pushing your limits and challenging the status quo, we have an opportunity for you. We are actively looking for an ingenious DFT Engineer based in Lausanne, Switzerland or the United Kingdom Key responsibilities: Hierarchical MBIST and scan insertion, BIST implementation, ATPG pattern generation, coverage analysis, convergence toward high coverage metrics; Pattern simulations with timing; Definition of timing constraints in test mode, timing report analysis and timing convergence; Development of accurate cycle-accurate functional patterns using the IJTAG methodology; Close work with test and production engineering teams to debug and bring devices into service during probe testing and final testing; Debugging silicon issues Skills: Excellent communication skills, and strong team spirit with a proactive attitude; Excellent debugging skills; Good scripting skills to develop automation Qualifications: More than 5 years of experience in DFT including implementation, test pattern development and simulation; Proven experience in contributing to DFT solutions for complex designs; Experience with IJTAG methodologies; Experience in hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies; Experience in ATPG pattern generation for different types of fault models, fault coverage analysis and convergence toward high coverage metrics; Good debugging capabilities in pattern simulation with timing; Experience with industry-standard EDA tools for DFT, timing and simulation; Knowledge of System Verilog Education: Bachelor's degree in electronic and electrical engineering, computer engineering (equivalent or higher)